Semiconductor integrated circuit apparatus, measurement result management system, and management server

ABSTRACT

A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement.

This is a divisional of U.S. application Ser. No. 11/847,712 filed onAug. 30, 2007, which is divisional application of U.S. application Ser.No. 10/926,364, filed on Aug. 26, 2004, which claims priority fromJapanese Patent Application No. 2003-302272, filed Aug. 27, 2003, andJapanese Patent Application No. 2004-172099, filed Jun. 10, 2004, theentire disclosures of said applications are incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitapparatus, and more particularly to a technology for measuring andmanaging a physical amount that exerts an influence upon an operation ofa semiconductor integrated circuit.

Generally, when the semiconductor integrated circuit apparatus(high-speed LSI) packed on a system failed, the system having it mountedcomes not to operate normally in some cases, and the system down occursin some cases, which causes the operation of system to stop. For this,various inspections are made to improve performance and quality of thehigh-speed LSI so that the high-speed LSI under operation does not fail.

As one of general inspection methods, there is a method of using a BIST(Built-In Self Test) for inspection (for example, a patent document 1).In the patent document 1, a technology was disclosed of providing a BISTfunction in a send unit, a receive unit, a control unit, and a centrallogical unit to inspect a signal interconnection. Further, a technologyof using the BIST for inspection to manage an inspection result was alsoproposed (for example, a patent document 2).

Also, there is a method of making an inspection by specifying factorsthat cause performance of the semiconductor integrated circuit todecline.

For example, in designing the high-speed LSI of late years, power sourcenoise and clock jitter are listed as a main factor of hinderingperformance improvement. So as to measure such power source noise andclock jitter, an inspection is made by making a probing measurement fromthe outside of the LSI to evaluate a power source noise waveform and apeak value of the clock jitter.

Further, as a factor of hindering the performance improvement other thanthe foregoing, a malfunction in a step of assembling a semiconductorapparatus is listed. So as to prevent a decline in performance andquality that stems from the malfunction in a step of assembling thesemiconductor apparatus, there is a method of inspecting thesemiconductor integrated circuit to analyze the step in which the causeof the performance decline originates, and of stopping a manufacturingapparatus of its step, or adjusting the manufacturing apparatusresponding to a necessity (for example, a patent document 3).

Also, as a malfunction of the high-speed LSI, degradation that comes outas an operating hour elapses is listed. A technology for integrating theoperating hour in order to recognize a degradation situation etc. wasalso proposed (for example, a patent document 4).

Yet further, a technology of, by monitoring power consumption, makingmanagement so that no malfunction occurred was also proposed (forexample, a patent document 5).

[PATENT DOCUMENT 1] Laid-Open of PCT translation No. 2003-529145

[PATENT DOCUMENT 2] JP-P1999-31399A

[PATENT DOCUMENT 3] JP-P1996-195406A

[PATENT DOCUMENT 4] JP-P1993-326845A

[PATENT DOCUMENT 5] JP-P2003-7838A

The above-mentioned prior arts, however, accompanied the followingproblems.

In a case of using the BIST for inspection like the patent document 1 orthe patent document 2, there was a case where the malfunction occurredbeyond its prediction in the actual operation because test data wasprepared responding to its use situation for inspection. Also, it wasdifficult to predict the noise or the jitter in designing.

Further, in a case of using the BIST for inspection, there was no chancethat the semiconductor integrated circuit other than the semiconductorintegrated circuit that was an object of measurement operated actually(a stop state etc.), so when it was caused to operate actually, itreceived an influence from the other semiconductor integrated circuitapparatus, and failed in some cases.

Also, the factor that causes the performance of the semiconductorintegrated circuit to decline is not only one factor, and there was alsoa case where various factors were piled upon, and the performancedeclined. For this, in a case where the various factors were piled up,and the performance declined, its factors were impossible to analyze andremove because the inspection item (measurement content) was limited toa specified one in the foregoing prior art.

Further, in a case of measuring the noise or the jitter, the noise orthe jitter on the LSI was impossible to measure in the high-speed LSI.Its reason is that a high-speed signal on the LSI is impossible tooutput to the outside of the LSI because a band degrades due to a pad ora pin of a package. Also, even though the probing measurement wasemployed, it was difficult to make a probing measurement of the justneighborhood of a point that is required to measure in the package ofnumerously employed flip-chips in the high-speed LSI.

Further, the problem lay in that it was difficult to predict the noiseor the jitter that exerted an influence upon the operation of thesemiconductor integrated circuit in designing, and in addition hereto,it was very difficult to reduce the noise or the jitter aftermanufacturing the LSI. With the noise, in a case where it was found thatthe power source noise was excessive after manufacturing the LSI, theproblem existed that adding the LSI having an on-chip decouplingcapacity that was a countermeasure to the power source noise gave riseto high cost and delay in development. With the jitter, as a parameterthat exerts an influence upon the jitter of a phase-locked loop(hereinafter, referred to as a PLL) for generating a clock signal, thereare a resistance value or a capacity value of a loop filter configuringthe PLL, a gain of a voltage control oscillator, a current value of apower source of a charge pump circuit, and a frequency dividing numberof a divider. However, the parameter was impossible to decide clearlybecause the actual jitter value was unknown, whereby it was verydifficult to design the PLL having low jitter.

Further, it was difficult to find a countermeasure for lowering thenoise and the jitter that were main factors exerting an influence uponthe operation of the semiconductor integrated circuit. For example, as arule, the cause of the jitter originates in the power source noise, anda strong correlation exists between the jitter and the power sourcenoise. Accordingly, so as to reduce the jitter, the power source noisehas to be reduced. So as to reduce the power source noise, a powersource system of anyone of a board, the package, and the LSI has to bemodified. As shown in FIG. 46, the low-frequency power source noise isdecided by the power source system of the board, theintermediate-frequency power source noise is decided by the power sourcesystem of the package, and the high-frequency power source noise isdecided by the power source system of the LSI. However, in theconventional evaluation of the peak value of the jitter and the waveformof the power source noise, it was impossible to clearly know whichportion of the power source system had to be corrected, so there was nochoice but take a countermeasure on a trial and error basis, which waspoor in efficiency.

DISCLOSURE OF THE INVENTION

The present invention has been accomplished in consideration of theabove-mentioned problems, and a first objective thereof is to make itpossible to measure the factors, which exert an influence upon theoperation of the semiconductor integrated circuit, such as the noise orthe jitter on the LSI that is actually working.

Also, a second objective thereof is to make it possible to reduce thevarious factors, which exert an influence upon the operation of thesemiconductor integrated circuit, such as the noise or the jitter evenafter manufacturing the LSI.

Further, a third objective thereof is to make it possible to efficientlyfind a countermeasure for reducing the various factors, which exert aninfluence upon the operation of the semiconductor integrated circuit,such as the noise or the jitter.

Further, a fourth objective thereof is to make it possible to preventthe operational stop of the system beforehand by measuring andmonitoring the various factors, which exert an influence upon theoperation of the semiconductor integrated circuit, such as the noise orthe jitter on the LSI that is actually working.

Further, a fifth objective thereof is that measuring and managing thevarious factors, which exert an influence upon the operation of thesemiconductor integrated circuit, such as the noise or the jitter on theLSI that is actually working makes it possible to reflect itsmeasurement and management in the next-generation semiconductorintegrated circuit.

A first invention for solving the above-mentioned problems, which is asemiconductor integrated circuit apparatus, is characterized in having:

a main frame circuit that is an object of measurement; and

a measurement circuit arranged on an identical chip to that of said mainframe circuit, said main frame circuit measuring a physical amount ofsaid main frame circuit when said main frame circuit works actually.

A second invention for solving the above-mentioned problems ischaracterized in that said main frame circuit operates at any time whensaid measurement circuit is performing a measurement operation in theabove-mentioned first invention.

A third invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring jitter information of said main frame circuit in theabove-mentioned first invention.

A fourth invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring noise information of said main frame circuit in theabove-mentioned first invention.

A fifth invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring temperature information of said main frame circuit in theabove-mentioned first invention.

A sixth invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring power source information of said main frame circuit in theabove-mentioned first invention.

A seventh invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring power information of said main frame circuit in theabove-mentioned first invention.

An eighth invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring stress information of said main frame circuit in theabove-mentioned first invention.

A ninth invention for solving the above-mentioned problems ischaracterized in that said measurement circuit is a measurement circuitfor measuring device performance of said main frame circuit in theabove-mentioned first invention.

A tenth invention for solving the above-mentioned problems ischaracterized in that the physical amount that said measurement circuitmeasures is at least one of jitter information, noise information,temperature information, power source information, power information,stress information, and information of device performance at the time ofthe actual operation of said main frame circuit in the above-mentionedfirst invention.

An eleventh invention for solving the above-mentioned problems ischaracterized in providing said measurement circuit in plural on anidentical chip in the above-mentioned first invention.

A twelfth invention for solving the above-mentioned problems ischaracterized in having analysis means for analyzing the physical amountthat exerts an influence upon the actual operation of said main framecircuit, based upon the physical amount that said measurement circuitmeasured in the above-mentioned first invention.

A thirteenth invention for solving the above-mentioned problems ischaracterized in providing said analysis means on an identical chip tothat of said main frame circuit and said measurement circuit in theabove-mentioned twelfth invention.

A fourteenth invention for solving the above-mentioned problems ischaracterized in providing said analysis means outside the chip havingsaid main frame circuit and said measurement circuit provided in theabove-mentioned twelfth invention.

A fifteenth invention for solving the above-mentioned problems ischaracterized in providing transfer means for transferring saidmeasurement result of said measurement circuit to said analysis means onan identical chip to that of said main frame circuit and saidmeasurement circuit in the above-mentioned thirteenth invention.

A sixteenth invention for solving the above-mentioned problems ischaracterized in providing transfer means for transferring a measurementresult of said measurement circuit to said analysis means that wasprovided outside on an identical chip to that of said main frame circuitand said measurement circuit in the above-mentioned fourteenthinvention.

A seventeenth invention for solving the above-mentioned problems ischaracterized in that in a case where at least one main frame circuit isprovided on said chip, and yet a plurality of the measurement circuitsare provided, said analysis means is configured to receive themeasurement results from a plurality of the measurement circuits, and toanalyze the physical amount that exerts an influence upon the actualoperation of the main frame circuit in the above-mentioned twelfthinvention.

An eighteenth invention for solving the above-mentioned problems ischaracterized in having accumulation means for accumulating saidmeasurement results of said measurement circuit in the above-mentionedfirst invention.

A nineteenth invention for solving the above-mentioned problems ischaracterized in providing said accumulation means on an identical chipto that of said main frame circuit and said measurement circuit in theabove-mentioned eighteenth invention.

A twentieth invention for solving the above-mentioned problems ischaracterized in providing said accumulation means outside the chiphaving said main frame circuit and said measurement circuit provided inthe above-mentioned eighteenth invention.

A twenty-first invention for solving the above-mentioned problems ischaracterized in that, in said accumulation means, said measurementresult of said measurement circuit, and measurement information forspecifying a measurement time, a measurement position, or a measurementstatus of said measurement result of said measurement circuit are storedcorrespondingly in the above-mentioned eighteenth invention.

A twenty-second invention for solving the above-mentioned problems ischaracterized in that said measurement information is a measurementresult that a measurement circuit other than said measurement circuitmeasured in the above-mentioned twelfth invention.

A twenty-third invention for solving the above-mentioned problems ischaracterized in having analysis means for analyzing the physical amountthat exerts an influence upon the actual operation of said main framecircuit based upon said measurement information in the above-mentionedtwelfth invention.

A twenty-fourth invention for solving the above-mentioned problems ischaracterized in having monitor means for giving a fault warning of saidmain frame circuit based upon said analysis of said analysis means inthe above-mentioned twelfth invention.

A twenty-fifth invention for solving the above-mentioned problems ischaracterized in having improvement means for improving the physicalamount that exerts an influence upon said main frame circuit based uponsaid analysis result of said analysis means in the above-mentionedtwelfth invention.

A twenty-sixth invention for solving the above-mentioned problems ischaracterized in having amount reduction means for reducing informationcontent of said measurement result of said measurement circuit in theabove-mentioned first invention.

A twenty-seventh invention for solving the above-mentioned problems,which is a measurement result management system, is characterized inhaving:

a semiconductor integrated circuit apparatus having:

-   -   a main frame circuit that is an object of measurement;    -   a measurement circuit arranged on an identical chip to that of        said main frame circuit, said main frame circuit measuring a        physical amount of said main frame circuit at the time of an        actual operation of said main frame circuit; and    -   transmission means for transmitting said measurement    -   result of said measurement circuit, and

identification information for uniquely identifying said main framecircuit; and

a management server having:

-   -   reception means for receiving said transmitted measurement        result and identification information; and    -   management means for managing said received measurement result        identification information by identification information.

A twenty-eighth invention for solving the above-mentioned problems ischaracterized in that said transmission means have encryption means forencrypting the measurement result and the identification information foruniquely identifying said main frame circuit in the above-mentionedtwenty-seventh invention.

A twenty-ninth invention for solving the above-mentioned problems ischaracterized in that said reception means have decoding means fordecoding the transmitted measurement result and identificationinformation in the above-mentioned twenty-eighth invention.

A thirtieth invention for solving the above-mentioned problems ischaracterized in that said management server has monitor means forgiving a fault warning of said main frame circuit based upon themeasurement result that said management means manage in theabove-mentioned twenty-seventh invention.

A thirty-first invention for solving the above-mentioned problems, whichis a management server arranged on an identical chip to that of a mainframe circuit that is an object of measurement, said management servermanaging a measurement result of said measurement circuit that istransmitted from a semiconductor integrated circuit apparatus having ameasurement circuit for measuring a physical amount of said main framecircuit at the time of an actual operation of said main frame circuit,is characterized in having:

reception means for receiving the transmitted measurement result, andidentification information for uniquely identifying said main framecircuit; and

management means for managing said received measurement resultidentification information by identification information.

A thirty-second invention for solving the above-mentioned problems ischaracterized in that in a case where the transmitted measurement resultand identification information were encrypted, said reception means havedecoding means for decoding the encrypted measurement result andidentification information in the above-mentioned thirty-firstinvention.

A thirty-third invention for solving the above-mentioned problems ischaracterized in that said management server has monitor means forgiving a fault warning of said main frame circuit based upon themeasurement result that said management means manage in theabove-mentioned thirty-second invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual view of the semiconductor integrated circuitapparatus of the present invention;

FIG. 2 is a block diagram of the measurement circuit in a firstembodiment;

FIG. 3 is a block diagram of a delay generator 10;

FIG. 4 is a block diagram of a phase comparator 11;

FIG. 5 is a view for explaining a method of measuring the period of theclock signal;

FIG. 6 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a peak value holding circuit was provided;

FIG. 7 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a low-pass filter was provided;

FIG. 8 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a serialization circuit was provided;

FIG. 9 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a memory circuit was provided;

FIG. 10 is a conceptual view of the semiconductor integrated circuitapparatus in a case where an analysis section and a monitor section wereprovided;

FIG. 11 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a transfer section was provided;

FIG. 12 shows a process flow of the measurement result in the presentinvention;

FIG. 13 is a graph showing time dependent of the clock period andfrequency dependent of the clock period;

FIG. 14 is a conceptual view of the semiconductor integrated circuitapparatus in a case where an adjustment circuit was provided;

FIG. 15 is a conceptual view of the semiconductor integrated circuitapparatus in a case of reducing the jitter;

FIG. 16 is a configuration view of a PLL circuit in the presentinvention;

FIG. 17 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a D/A converter and an A/D converter wereprovided;

FIG. 18 is a conceptual view of the semiconductor integrated circuitapparatus in a case where a power source filter was provided;

FIG. 19 is a block diagram illustrating a second embodiment of thepresent invention;

FIG. 20 is a block diagram of a delay generator in a third embodiment ofthe present invention;

FIG. 21 is a view for explaining a method of measuring the period of theclock signal in the third embodiment of the present invention;

FIG. 22 is a block diagram illustrating a fourth embodiment of thepresent invention;

FIG. 23 is a block diagram illustrating a fifth embodiment of thepresent invention;

FIG. 24 is an explanatory view illustrating an operation of the fifthembodiment of the present invention;

FIG. 25 is a block diagram illustrating a sixth embodiment of thepresent invention;

FIG. 26 is a circuit diagram of a high-pass filter of the presentinvention;

FIG. 27 is a circuit diagram of a voltage comparator of the presentinvention;

FIG. 28 is an explanatory view illustrating an operation of the voltagecomparator in a case where a sampling signal is at a high level;

FIG. 29 is an explanatory view illustrating an operation of the voltagecomparator in a case where a sampling signal is at a low level;

FIG. 30 is a conceptual view of the semiconductor integrated circuitapparatus in a case of reducing the noise in the present invention;

FIG. 31 is a block diagram of the adjustment circuit for reducing thenoise in the present invention;

FIG. 32 is a block diagram of the adjustment circuit for reducing thenoise in the present invention;

FIG. 33 is a block diagram illustrating a seventh embodiment of thepresent invention;

FIG. 34 is a block diagram illustrating an eighth embodiment of thepresent invention;

FIG. 35 is a block diagram illustrating a ninth embodiment of thepresent invention;

FIG. 36 is an explanatory view illustrating an operation of the ninthembodiment of the present invention;

FIG. 37 is a block diagram illustrating a tenth embodiment of thepresent invention;

FIG. 38 is a view of an inverter circuit;

FIG. 39 shows a layout pattern A of the inverter circuit;

FIG. 40 shows a layout pattern B of the inverter circuit;

FIG. 41 shows an installation example of the measurement circuit;

FIG. 42 shows an example of an output signal;

FIG. 43 is a block diagram illustrating a twelfth embodiment of thepresent invention;

FIG. 44 is a block diagram illustrating a thirteenth embodiment of thepresent invention;

FIG. 45 is a block diagram illustrating a fourteenth embodiment of thepresent invention; and

FIG. 46 is an equivalent circuit diagram of the power source system.

DETAILED DESCRIPTION OF THE EMBODIMENTS

As to the semiconductor integrated circuit of the present invention,configuring the semiconductor integrated circuit that is actuallyoperating, which is an object of measurement, and the measurementcircuit for measuring the physical amount, which exerts an influenceupon the actual operation of the semiconductor integrated circuit, suchas the jitter or noise jitter and the noise of this semiconductorintegrated circuit on the identical chip allows an objective of thepresent invention to be accomplished.

Also, feeding the measurement result of the measurement circuit of thepresent invention back to the circuit for adjusting the semiconductorintegrated circuit that is an object of measurement allows an objectiveof the present invention to be accomplished.

Embodiment 1

A first embodiment in the present invention will be explained.

FIG. 1 is a conceptual view of the semiconductor integrated circuitapparatus in the present invention.

A semiconductor integrated circuit 131 in accordance with the presentinvention, i.e. the measurement circuit is mounted inside asemiconductor integrated circuit apparatus 130.

The measurement circuit is arranged on an identical chip to that of thesemiconductor integrated circuit that is an object of measurement.Further, the measurement circuit measures the physical amount thatexerts an influence of the operation of the semiconductor integratedcircuit that is actually operating. Additionally, as to the so-calledchip in the present invention, in addition to one chip having a minimumunit, for example, let a SiP (System in Package) and a three-dimensionalLSI which become a one-unit chip by connecting a plurality of the chipswith a high-speed signal wiring be defined as one chip. Also, theso-called actual operation of the semiconductor integrated circuitsignifies a status where the power source was input into a terminal ofthe chip having this semiconductor integrated circuit mounted. And, thisterminal is not a terminal such as a test terminal that is employedtemporarily in testing.

The measurement circuit in the present invention will be explained.

Additionally, in this embodiment, a case will be explained where themeasurement circuit for measuring fluctuation of the period (periodicjitter) of the clock signal within the semiconductor integrated circuitwas realized by employing a technology of a power source voltage of 1.0V and a 90-nm CMOS process. Also, in this embodiment, the clock signalof the semiconductor integrated circuit is employed for explanation as asignal that is an object of measurement; however it is not limitedhereto. For example, it should be a data signal that the semiconductorintegrated circuit outputs.

FIG. 2 is a block diagram of the measurement circuit in the firstembodiment.

As shown in FIG. 2, the measurement circuit 130 is configured of a delaygenerator 10, a phase comparator 11, and a calibrator 17.

A two-GHz clock signal 18 of the semiconductor integrated circuit thatis an object of measurement, and a four-bit delay adjustment signal 32from the calibrator 17 are input into the delay generator 10. The clocksignal 18 is a clock signal that passes through the semiconductorintegrated circuit that is actually operating. Also, in this embodiment,assume that this clock signal was set to 2 GHz in designing thesemiconductor integrated circuit.

A block diagram of the delay generator 10 is shown in FIG. 3. As shownin FIG. 3, the delay generator 10 is configured of a fixed delay section30 of 20 ps, and a phase interpolator 31. And, the four-bit delayadjustment signal 32 from the calibrator 17 is input into the fixeddelay section 30.

The delay generator 10 is for outputting 64 delay signals of the clocksignal 18 partitioned 5 ps by 5 ps in a range from 340 ps to 660 ps. Asto the delay signals that are delayed 5 ps by 5 ps, its delay signal isgenerated by employing the phase interpolator 31 because its delay issmaller than a delay (10 ps) per one stage of the inverter.Specifically, by inputting the fixed delay of 20 ps into a first-stagephase interpolator 34, a delay signal having a partition of 10 ps thatis half 20 ps is generated, and by inputting this into a second-stagephase interpolator 35, a delay signal having a partition of 5 ps that isa half of 10 ps is generated.

Continuously, the phase comparator 11 will be explained.

An output 33 of the delay generator, and the clock signal 18 are inputinto the phase comparator 11.

A configuration of the phase comparator 11 is shown in FIG. 4.

The phase comparator 11 is configured of 64 flip-flops 36. 64 outputs 33of the delay signal output from the delay generator 10 are connected todata inputs of respective flip-flops, and the clock signal 18 that is anobject of measurement is connected to a clock input of each flip-flop.

The phase comparator 11 is for determining which edge rose ahead, out ofa leading edge of the clock signal 18 that is an object of measurement,and each leading edge of the output 33 of the delay generator 10. In acase where the leading edge of the output 33 of the delay generatorrises ahead of the leading edge of the clock signal 18 that is an objectof measurement, the flip-flop 36 outputs a high-level signal. In a casewhere the leading edge of the output 33 of the delay generator risesbehind the leading edge of the clock signal 18 that is an object ofmeasurement, the flip-flop 36 outputs a low-level signal. Accordingly,employing the flip-flop 36 makes it possible to determining which edgerose ahead, out of the leading edge of the clock signal 18 that is anobject of measurement, and each leading edge of the output 33 of thedelay generator.

Herein, by employing FIG. 5, a method of, by using the foregoing delaygenerator 10 and phase comparator 11, measuring the period of the clocksignal will be explained.

As shown in FIG. 5, 64 leading edges of the output 33 of the delaygenerator output from the delay generator 10 exist at an equal intervalof a 5-ps partition in a range of 340 ps up to 660 ps, with a firstleading edge 40 of the clock signal 18 that is an object of measurementassumed to be a starting point. Determining which side rose ahead, outof a second leading edge 41 of the clock signal 18 that is an object ofmeasurement, and each of 64 leading edges having a 5-ps partition of theoutput 33 of the delay generator output from the delay generator 10 byeach of 64 flip-flops 36 allows the period of the clock signal to bemeasured 5-ps partition by 5-ps partition in a range of 500 ps±660 ps.This allows the period of the clock signal including the jitter to bemeasured.

As an example, an ideal case where no jitter exists in the clock signal18 that is an object of measurement will be explained.

With the first leading edge 40 of the clock signal 18 that is an objectof measurement assumed to be a starting point, the second leading edge41 of the two-GHz clock signal 18 of that is an object of measurementexists after 500 ps. The time ranging from the first leading edge 40 tothe second leading edge 41 is a period of the cock signal.

With the first leading edge 40 of the clock signal 18 that is an objectof measurement assumed to be a starting point, the outputs 33 of thedelay generator that rose in a range of 340 ps to 500 ps are ahead ofthe second leading edge 41 of the clock signal 18 that is an object ofmeasurement. For this, the output level of each flip-flop becomes high,and only the high-level signal is output to outputs A [31:0] of thephase comparator 11.

On the other hand, with the first leading edge 40 of the clock signal 18that is an object of measurement assumed to be a starting point, theoutputs 33 of the delay generator that rose in a range of 500 ps up to600 ps are behind the second leading edge 41 of the clock signal 18 thatis an object of measurement. For this, the output level of eachflip-flop becomes low, and only the low-level signal is output tooutputs A [63:32] of the phase comparator 11.

Accordingly, in the outputs A [63:0] of the phase comparator 11, a mostsignificant bit A [31] having the high-level signal output correspondsto a period 500 ps of the clock signal that is an object of measurement.

In a case of a practical signal, i.e. in a case where the jitter existsin the clock signal, if the period of the clock signal is shorter than500 ps, the most significant bit having the high-level signal outputbecomes one of A [30] to A [0], and if the period of the clock signal islonger than 500 ps, the most significant bit having the high-levelsignal output becomes one of A [33] to A [63]. This measurement resultis output as a 64-bit digital signal.

Continuously, a priority encoder 12 will be explained for reducing adata amount of the measurement result measured by the foregoingmeasurement circuit.

So as to output all of 64 outputs A [63:0] from the phase comparator 11of the foregoing measurement circuit as a measurement result, 64 outputpins have to be prepared, which causes the cost to become high.Thereupon, so as to reduce the output number, the priority encoder 12 isused.

In the 64 outputs A [63:0] of the phase comparator 11, the mostsignificant bit having the high level signal output is most importantbecause of signifying the period of the clock signal 18 that is anobject of measurement. On the other hand, the bits that are ranked lowthan the most significant bit having the high-level signal output areall a high-level signal, and the bits that are ranked high than the mostsignificant bit having the high-level signal output are all a low-levelsignal. For this, the output signal other than the most significant bithaving the high-level signal output can be predicted. Thereupon, only abit position of the most significant bit having the high-level signaloutput is binary-coded and is output by the priority encoder 12.

This output of the priority encoder 12 is input into a peak valueholding circuit 13 and a digital low-pass filter 14 respectively.

The priority encoder 12 is a circuit for making a binary coding of andoutputting the bit position of the most significant bit having thehigh-level signal output.

Employing the priority encoder 12 makes it possible to curtail the 64outputs of the phase comparator 11 into a six-bit output.

17 is a calibrator.

As described above, the delay generator 10 outputs 64 delays partitioned5 ps by 5 ps in a range of 340 ps to 660 ps. However, delay fluctuationoccurs due to process dispersion, power source voltage fluctuation, anda temperature change in the practical LSI. For this, it is verydifficult to realize the delay as designed. When the delay fluctuationexists, an accuracy of the value of the jitter of the measurement resultis lost, which becomes a subject of discussion. Thereupon, a necessityoccurs for correcting the delay fluctuation due to the processdispersion, the power source voltage fluctuation, and the temperaturechange.

Also in a case where the jitter exists in the two-GHz clock signal 18that is an object of measurement, an average value of the clock periodamounts to 500 ps. Accordingly, in a case where the delay as designedwas realized in the delay generator 10, the probability that the levelof the most significant bit of the output of the priority encoder 12becomes high is less than 50%. However, in a case where the delay of thedelay generator 10 is shorter than the designed one, the probabilitythat the level of the most significant bit of the output of the priorityencoder 12 becomes high is 50% or more. Conversely, in a case where thedelay of the delay generator 10 is longer than the designed one, theprobability that the level of the most significant bit of the output ofthe priority encoder 12 becomes high is less than 50%.

Accordingly, checking whether the level of the most significant bit ofthe output of the priority encoder 12 is high or low plural times makesit possible to determine whether the delay of the delay generator 10 islonger or shorter than the designed one. It is the calibrator 17 thatrealizes the delay as designed in the delay generator 10 by feeding thisdetermination result back to the delay generator 10.

As shown in FIG. 2, a reset signal 20, the clock signal 18 that is anobject of measurement, and the most significant bit that is an output ofthe priority encoder 12 are input into the calibrator 17. The calibrator17 outputs a delay adjustment signal 32 to the delay generator 10.

Also, the calibrator 17 carries out a calibration only once ininitiating the measurement. By inputting the reset signal 20 into thecalibrator 17, an calibration operation is initiated to initialize adelay adjustment signal 32 B [3:0] into (1000). During the calibrationoperation, it checks whether the provability that the level of the mostsignificant bit of the output of the priority encoder 12 becomes high is50% or more, or less than 50%. And, if the provability that the levelbecomes high is 50% or more, adding 1 to the delay adjustment signal 32B [3:0] causes the delay of the delay generator 10 to augment, and if itis less than 50%, subtracting the delay adjustment signal 32 B [3:0] by1 causes the delay of the delay generator 10 to decrease. Repeating thedelay determination and the delay adjustment 32 times in such a mannerallows the delay fluctuation due to the process dispersion, the powersource voltage fluctuation, and the temperature change to be corrected,which makes it possible to realize the delay as designed in the delaygenerator 10.

After the calibrator 17 repeated the delay determination and the delayadjustment 32 times, it holds the value of the delay adjustment signal32, and completes the calibration.

Continuously, the peak value holding circuit for outputting only thepeak value of the measurement result measured in the foregoingmeasurement circuit will be explained, by employing FIG. 6.

A circuit 144 for measuring the jitter in a time series basis, i.e. thephase comparator 11, and the peak value holding circuit 13 areconfigured in a measurement circuit 141 for measuring the jitter.Additionally, a case will be explained where the peak value holdingcircuit 13 is configured within the measurement circuit; however it maybe configured outside the measurement circuit. Also, the peak valueholding circuit 13 may be configured so that it is connected to theforegoing phase comparator 11 of the measurement circuit; however thepriority encoder 12 is preferably connected between the phase comparator11 and the peak value holding circuit 13. In this embodiment, aconfiguration having the priority encoder 12 connected is employed forexplanation.

The peak value holding circuit 13 holds the maximum value or the minimumvalue out of six-bit clock period measurement results that are outputfrom the priority encoder 12 to output it with a six-bit pattern. Thisallows the maximum value and the minimum value of the period of theclock including the periodic jitter to be measured. The peak valueholding circuit 13 holds the maximum value in a case where amaximum-value/minimum-value selection signal 21 is a high-level signal,and it holds the minimum value in a case where themaximum-value/minimum-value selection signal 21 is a low-level signal.The initialization of the maximum value or the minimum value that itholds is carried out with a peak-value reset signal 23 from thecalibrator 17.

In such a manner, employing the peak-value holding circuit makes itpossible to measure only the peak value of the jitter.

Continuously, a digital low-pass filter for deleting a high-frequencycomponent of the measurement result measured by the foregoingmeasurement circuit will be explained, by employing FIG. 7.Additionally, the low-pass filter is employed for explanation in thisembodiment; however a band pass filter may be employed.

A circuit 145 for measuring the jitter in a real time basis, i.e. thephase comparator 11, and a digital low-pass filter 14 are configured inthe foregoing measurement circuit 141 for measuring the jitter.Additionally, a case where the low-pass filter is configured within themeasurement circuit will be explained; however it may be configuredoutside the measurement circuit. Also, the digital low-pass filter 14may be configured so that it is connected to the phase comparator 11 ofthe foregoing measurement circuit; however the priority encoder 12 ispreferably connected between the phase comparator 11 and the digitallow-pass filter. Herein, a configuration having the priority encoder 12connected is employed for explanation.

As to the six-bit clock period measurement result that is output fromthe priority encoder 12, its data amount amounts to 12 G bps. In a caseof having the purpose of measuring the maximum value and the minimumvalue of the periodic jitter, the measurement result should be outputintermittently. However, in a case of analyzing a frequency component ofthe periodic jitter, the measurement result has to be outputcontinuously so that no data is left out.

So as to analyze the frequency component of the periodic jitter, in acase of outputting data of 12 G bps that is a clock period measurementresult to the outside of the measurement circuit, for example, 12 pinseach of which can send 1 G bps out have to be prepared, which causes thecost to become high. Thereupon, so as to curtail the pin number of theoutput, the high-frequency component of the measurement result isdeleted by employing the digital low-pass filter 14, which is output assix-bit data.

Specifically, by deleting the high-frequency component of themeasurement result of 12 G bps with a six-bit pattern by the digitallow-pass filter 14, the measurement result is curtailed into data of 1.5G bps that is eight times smaller than it. The band of the measurementresult is reduced from an original 1-GHz one to a 125-MHz one that iseight times smaller than it, and the component of 125 MHz to 1 GHz isdeleted; however the component of less than 125 MHz is preserved. Thisallows data to be reduced.

As described above, the band of the measurement result and the pinnumber of the output have a trade-off relation. For example, the highera cut-off frequency of the digital low-pass filter 14 is, the more thehigh-frequency component of the measurement result is output, wherebythe data amount augments, and the pin number of the output augments.Conversely, the cut-off frequency of the digital low-pass filter 14 islower, all the more only the low-frequency component of the measurementresult is output, whereby the data amount reduces, and the pin number ofthe output reduces.

Employing the low-pass filter in such a manner makes it possible tooutput the measurement result of the low-frequency component even thoughthe band of the measurement result is low.

Additionally, with a configuration having the foregoing peak-valueholding circuit 13 and digital low-pass filter 14 connected to themeasurement circuit, as shown in FIG. 2, its configuration is made sothat a selector 15 is provided to select and output the six-bit outputof the peak value holding circuit 13, or the six-bit output of thedigital low-pass filter 14.

Next, a configuration having a serialization circuit provided forreducing the data amount of the measurement result will be explained, byemploying FIG. 8.

A circuit 144 for measuring the jitter in a time series basis, i.e. thephase comparator 11, and a serialization circuit 16 are configured inthe forgoing measurement circuit 141 for measuring the jitter.Additionally, a case where the serialization circuit is configuredwithin the measurement circuit will be explained; however it may beconfigured outside the measurement circuit. Also, the serializationcircuit 16 may be configured so that it is connected to the phasecomparator 11 of the measurement circuit; however it is preferablyconfigured so that it is connected to the priority encoder 12, the peakvalue holding circuit 13, the digital low-pass filter 14, or theselector 15. In this embodiment, a configuration having theserialization 16 connected to the selector 15 is employed forexplanation.

The serialization circuit 16 is for converting an m-bit output into ann-bit one (m>n). In this embodiment, the six-bit output to be outputfrom the selector 15 is converted into a two-bit one, and is output.

In such a manner, providing the serialization circuit allows the numberof the output signal to be curtailed.

Next, a memory circuit for accumulating the measurement result that theforegoing measurement circuit measured will be explained, by employingFIG. 9.

A circuit 144 for measuring the jitter in a time series basis, i.e. thephase comparator 11, and a memory circuit 50 are configured in theforegoing measurement circuit 141 for measuring the jitter.Additionally, a case where the memory circuit is configured within themeasurement circuit will be explained; however it may be configuredoutside the measurement circuit, and further, not only it may beconfigured on the identical chip to that of the measurement circuit, butalso it may be configured outside the chip. Also, the memory circuit maybe configured to accumulate the output of the phase comparator 11 or theserialization circuit 16 of the foregoing measurement circuit; however aconfiguration is made more preferably so that the data amount is reducedby employing the foregoing priority encoder 12, peak value holdingcircuit 13 or digital low-pass filter 14 to causes the memory circuit tostore it because a capacity is limited. Also, the memory circuit may beconfigured to accumulate an analysis result by an analysis section to belater described.

The memory circuit 50 accumulates the measurement result of the jittermeasurement circuit and a measurement time of the measurement resultcorrespondingly. Further, the memory circuit 50 accumulates themeasurement result that the measurement circuit other than themeasurement circuit for measuring the jitter measured.

Configuring such a memory circuit eliminates a necessity for outputtingthe measurement result whenever the measurement is made. Also, it isenough that the measurement result is output at a low speed aftermeasurement, which enables that making the band of the measurementresult broad is compatible with reducing the pin number of the output19.

Next, the analysis section for analyzing the measurement result obtainedin the foregoing measurement circuit will be explained, by employingFIG. 10. Additionally, a case where the analysis section is configuredwithin the measurement circuit will be explained; however it may beconfigured outside the measurement circuit. Also, the analysis section150 may make an analysis based upon the output of the phase comparator11 or the serialization circuit 16 of the foregoing measurement circuit,and the measurement result of which the data amount was reduced byemploying the foregoing priority encoder 12, peak value holding circuit13, or digital low-pass filter 14; however an analysis is made morepreferably, based upon the data accumulated in the memory circuit 50.

The analysis section 150 is for analyzing the physical amount thatexerts an influence upon the operation of the semiconductor integratedcircuit, based upon the measurement result.

As one example of an analytical operation in the analysis section, amethod will be explained of analyzing the periodic jitter amount by theanalysis section.

The analysis section compares the period of the clock signal that isoutput from the serialization circuit 16 with the clock period set atthe time of designing the semiconductor integrated circuit, therebyanalyzing the periodic jitter amount.

Continuously, a case will be explained of measuring the maximum valueand the minimum value of the periodic jitter. Additionally, a case willbe explained herein of employing the output result from the peak valueholding circuit 13 for analysis.

In a case of measuring the maximum value and the minimum value of theperiodic jitter, it is enough that the analysis section samples themeasurement result of only one point at an arbitrary timing. This isbecause no change almost exists in the output result from the peak valueholding circuit 13 provided that many clock period measurement resultsof which the measurement number was, for example, approx. 10000 werealready input into the peak value holding circuit 13.

Accordingly, after the measurement circuit measured many clock periods,the analysis section samples the data output from the serializationcircuit 16 at an arbitrary timing. The analysis section compares themaximum value of the sampled measurement result, i.e. the maximum valueof the clock period of the clock signal 18 with the clock period set atthe time of designing the semiconductor integrated circuit, therebyanalyzing the maximum value of the periodic jitter. Similarly, theanalysis section compares the minimum value of the sampled measurementresult, i.e. the minimum value of the clock period of the clock signal18 with the clock period set at the time of designing the semiconductorintegrated circuit, thereby analyzing the minimum value of the periodicjitter.

Additionally, a case was explained herein of making an analysis basedupon the output from one measurement circuit; however a configurationmay be made so that a plurality of the measurement circuits are providedwithin the chip to respectively make an analysis based upon the outputsfrom a plurality of the measurement circuits. Also, not only theanalysis section is configured on the identical chip to that of themeasurement circuit, but also it may be configured outside the chip;however in a case where it is provided outside the chip, as shown inFIG. 11, a transfer section is provided, and the transfer section makestransmission to the analysis section.

Continuously, a case will be explained where the analysis sectionanalyzes the frequency component of the periodic jitter. Additionally, acase will be explained of employing the output result from the digitallow-pass filter 14 for analysis.

The analysis section for analyzing the frequency component of theperiodic jitter has a real-time oscilloscope and a personal computer.

Herein, a method of analyzing the frequency component of the periodicjitter of 1 MHz or more for the measurement result of the period of thetwo-GHz clock signal will be explained, by employing FIG. 12.

In a case of analyzing the frequency component of the periodic jitter,the measurement result has to be output continuously so that no data isleft out. For this, a real-time oscilloscope 44 measures all ofmeasurement results 43 of the period of the continuous clock signals ofwhich number is 2000 or more as digital data, and outputs its measureddata to a personal computer 45. Making a Fourier transform of thedigital data on the personal computer 45 allows a frequency component 46of the jitter to be obtained.

In FIG. 13, an example of time dependent of the clock period andfrequency dependent of the clock period is shown. An axis of ordinaterepresents the measurement result of the period of the clock signal,whereas an axis of abscissa represents the time (number of times). Threepeaks of a low frequency, an intermediate frequency, and a highfrequency exist in a graph of the frequency dependent of the period ofthe clock signal, and above all, the peak of the intermediate frequencyis largest. Accordingly, the instruction that the power source noise ofthe intermediate frequency should be reduced by modifying the powersource system of the package shown in FIG. 46 can be clearly obtainedbecause it is most important to reduce the jitter of the intermediatefrequency.

Additionally, the analysis section for analyzing the frequency componentof this periodic jitter is provided outside the chip, and the transfersection transmits the measurement result to the analysis section.

Next, a configuration having a monitor section for giving a faultwarning based upon the analyzed result will be explained.

As shown in FIG. 10, the monitor section, which is connected to theanalysis section, is for sending warning information out when it detectsabnormality. Additionally, a case will be explained where the monitorsection is configured within the measurement circuit; however it may beconfigured outside the measurement circuit.

One example of an operation of the monitor section will be explained.

When the jitter amount that the analysis section analyzed exceeds acertain value, the monitor section judges that abnormal dispersion wasdetected, and sends a malfunctional signal out to an MPU on theidentical chip. The MPU that received the malfunctional signal, forexample, causes a display section of the apparatus having thissemiconductor integrated circuit mounted to display the warninginformation in some cases, and notifies the warning information to amanager via a communication line (an internet, a mobile telephone,etc.). This warning information is identification information foridentifying the apparatus having this semiconductor integrated circuitmounted, the time when the abnormality was detected, fault predictioninformation, etc.

Next, a method will be explained of reducing the jitter based upon theanalyzed jitter.

As shown in FIG. 14, the semiconductor integrated circuit apparatus inthis embodiment is configured of a jitter measurement circuit 141, anadjustment circuit 147 for adjusting the noise or the jitter, and ameasured data process circuit 112. Additionally, this jitter measurementcircuit 141 includes the foregoing measurement circuit and analysissection.

A measurement result 148 obtained in the measurement circuit 141 isinput into the measured data process circuit 112. The measured dataprocess circuit 112 outputs a control signal 149 necessary for reducingthe jitter to the circuit 147 for adjusting the jitter.

Changing a parameter for exerting an influence upon the jitterdynamically with control signal 149 under a feedback control in a loopof the circuit 141 for measuring the jitter, the circuit 147 foradjusting the jitter, and the measured data process circuit 112 allowsthe jitter to be minimized.

Herein, one example of a method of reducing the jitter will beexplained.

As shown in FIG. 15, the semiconductor integrated circuit apparatus inthis embodiment is configured of a jitter measurement circuit 110, a PLL111 of the semiconductor integrated circuit that is an object ofmeasurement, and the measured data process circuit 112. A clock signal115 that the PLL 111 outputs is input into the jitter measurementcircuit 110. Additionally, this jitter measurement circuit 110 includesthe foregoing measurement circuit and analysis section.

A jitter measurement result 113 obtained in the jitter measurementcircuit 110 is input into the measured data process circuit 112. Themeasured data process circuit 112 judges and generates a control signal114 of the PLL necessary for reducing the jitter of the PLL 111 from thejitter measurement result 113, and outputs it to the PLL 111. Changing aparameter for exerting an influence upon the jitter dynamically with acontrol signal 114 of the PLL in a loop of the jitter measurementcircuit 110, the PLL 111, and the measured data process circuit 112makes it possible to take a feedback control so that the jitter isminimized.

Herein, one example of a method of changing a parameter for exerting aninfluence upon the jitter dynamically will be explained, by employingFIG. 16.

The PLL 111, which is configured of a phase comparator 1601 fordetecting a phase difference between two input signals, a charge pumpcircuit 1602 for converting a phase difference signal from the phasecomparator 1601 into an analogue signal from a digital signal, a loopfilter 1603, a divider 1604, and a voltage control oscillator 1605 ofwhich a oscillation frequency changes depending upon a voltage level ofa frequency control signal, configures a feedback loop.

At first, the phase comparator 1601 detects a phase difference betweenthe input signal, and the output signal of the voltage controloscillator 1605. The charge pump circuit 1602 and the loop filter 1603cause the input voltage level of the voltage control oscillator to go upand down based upon this phase difference. In a stationary state, thefrequency of the signal obtained by dividing the oscillation frequencyof the voltage control oscillator 1605 by the divider 1604 coincideswith the frequency of the input signal. That is, in a stationary state,a signal having the oscillation frequency obtained by increasing that ofthe input signal by a factor of N is obtained from the output.

Herein, the PLL 111 has a loop bandwidth that is decided by lcpKvco*R/N. Additionally, lcp is a design parameter of the charge pumpcircuit, Kvco is a design parameter of the voltage control oscillator1605, R is a design parameter of the loop filter, and N is a frequencydividing rate of the divider 1604. When this loop bandwidth is high, thehigh frequency component of the jitter that occurs in the voltagecontrol oscillator 1605 can be suppressed at the moment that the powersource of the PLL 111 fluctuated.

Accordingly, in a case where it was analyzed that the jitter of theintermediate frequency or the high frequency was larger, based uponinformation of the high frequency component that analysis meansanalyzed, enlarging the design parameter lcp of the charge pump circuitso that the loop bandwidth of the PLL 111 becomes high makes it possibleto improve jitter proof stress against the power source voltagefluctuation of the PLL 111. And, as a result, reduction of the jitter ofthe clock signal is made possible.

Employing the foregoing configuration allows the jitter of the cocksignal 115 to be reduced in this embodiment as compared with theconventional method of deciding and settling all parameters at the timeof designing the PLL.

Additionally, the jitter that the foregoing measurement circuit of thisembodiment measures is of analogue amount. For this, there is a case ofinputting or outputting the analogue voltage in order to measure thejitter. However, it is difficult to cause the analogue voltage topropagate on the LSI because the analogue voltage degrades due to thenoise. Thereupon, as shown in FIG. 17, by making a configuration so thatan input 79 is connected to a D/A converter 73 and an output 19 isconnected to an A/D converter 62, both signals of the input 79 and theoutput 19 may be converted indo a digital signal respectively in thecircuit 141 for measuring the jitter.

Also, as shown in FIG. 18, the foregoing measurement circuit of thisembodiment may be configured to use a power source line 121 and agrounding conductor 146 that are identical to that of the semiconductorintegrated circuit 140 that is an object of measurement. Inserting apower source filter 91 between the power source line 121 and themeasurement circuit 141 in such a manner allows the power source noiseto be prevented from breaking into the measurement circuit 141. Thiseliminates a necessity for a dedicated power source supply to thecircuit 141 for measuring the noise or the jitter, which enables thecost to become low.

As described above, mounting the measurement circuit in accordance withthe present invention inside the semiconductor integrated circuitapparatus enables measurement of the jitter on the LSI. Further, itbecomes possible to reduce the jitter on the LSI even aftermanufacturing the LSI, and to efficiently find a countermeasure forreducing the jitter in the semiconductor integrated circuit apparatusbased upon its obtained measurement result.

Embodiment 2

Next, a second embodiment in the present invention will be explained, byemploying FIG. 19.

In the foregoing measurement circuit of the first embodiment, theconfiguration was explained of, in outputting the data of 12 G bps tothe outside of the measurement circuit, deleting the high frequencycomponent of the measurement result of the period of the clock signal 18that was an object of measurement with the digital low-pass filter 14 toconvert and output the six-bit data into the two-bit one in theserialization circuit 16. In the second embodiment, a configurationhaving the digital low-pass filter 14 replaced with a memory circuit 50will be explained. Additionally, identical codes are affixed tocomponents similar to that of the first embodiment, and detailedexplanation thereof is omitted.

FIG. 19 is a block diagram of the measurement circuit of the secondembodiment in the present invention.

The memory circuit 50 stores the measurement result of 12 G bps that isan output of the priority encoder 12 for a constant time. Afterfinishing the measurement, responding to a request for transmitting themeasurement result, data that the memory circuit 50 stored istransmitted to the serialization circuit 16. The serialization circuit16 converts the transmitted six-bit data into a one-bit one, and outputsit at a low-speed data rate.

In such a manner, in a case where the digital low-pass filter 14 wasused, the band of the measurement result and the pin number of theoutput had a trade-off relation; however employing the memory circuit 50eliminates a necessity for sending the measurement result out to theoutside of the measurement circuit during the measurement, which enablesthat making the band of the measurement result broad is compatible withreducing the pin number of the output.

Embodiment 3

Next, a third embodiment in the present invention will be explained.

As a problem of the foregoing measurement circuit is listed the factthat the periodic jitter that occurred in the delay generator 10 shownin FIG. 2, which is superposed upon the periodic jitter of the clocksignal 18 that is an object of measurement, results in being added tothe analyzed periodic jitter. Accordingly, a difference has to beclarified between the periodic jitter that occurred in the delaygenerator 10 and the periodic jitter of the clock signal 18 that is anobject of measurement. Thereupon, in the third embodiment, so as to findonly the jitter amount of the clock signal 18 that is an object ofmeasurement, a configuration will be explained in which the period of aone-period portion and the period of a two-period portion of the clocksignal can be measured.

Assume that a periodic jitter (Jclk) of the clock signal 18 that is anobject of measurement, and a periodic jitter (Jdelay) that occurred inthe delay generator 10 are an independent phenomenon respectively, itfollows that a result (Jmeas) of the analyzed periodic jitter isexpressed in EQ. 1.

J _(meas)=√{square root over (J _(clk) ² +J _(delay) ²)}  [EQ. 1]

As a rule, upon increasing the delay of the delay generator 10 by afactor of n, the periodic jitter that occurred in the delay generator isalso increased by a factor of n. Let the analysis result of the periodicjitter in this case be defined as Jmeas_n, it is expressed in EQ. 2.

J _(meas) _(—) _(n)=√{square root over (J _(clk) ²+(n·J_(delay))²)}  [EQ. 2]

Jmeas and Jmeas_n can be measured; however Jclk and Jdelay, which areimpossible to measure, are an unknown quantity respectively. Thereupon,at first, out of outputs 33 of the delay generator 10 in the foregoingmeasurement circuit, two kinds of the period are measured by employingthe delay signals having different delays to analyze the periodic jitterbased upon its measurement result. And, solving simultaneous equationsof EQ. 1 and EQ. 2 enables the periodic jitter (Jclk) of the clocksignal 18 that is an object of measurement, and the periodic jitter(Jdelay) that occurred in the delay generator 10 to be calculated. Thismethod makes it possible to exclude an influence of the periodic jitterthat occurred in the delay generator 10 from the measurement result ofthe jitter, and to find only the periodic jitter of the clock signal 18that is an object of measurement.

Herein, the delay generator 10 in this embodiment will be explained, byemploying FIG. 20.

As shown in FIG. 20, the delay generator 10 is configured of a fixeddelay section 30 of 20 ps, a phase interpolator 31, and a selector 15. Abig difference with the delay generator 10 of FIG. 3 lies in that thedelay generator 10 has means added not only for measuring the clockperiod of a one-period portion of the 2-GHz clock that is an object ofmeasurement of the periodic jitter, but also for measuring the clockperiod of a two-period portion. The selector 15 is for making aselection as to whether the clock period of a one-period portion ismeasured, or the clock period of a two-period portion is measured.

The delay generator 10 in this embodiment comprises a one-period mode 51for outputting 64 delays partitioned 5 ps by 5 ps in a range of 340 psup to 660 ps, and a two-period mode 52 for outputting 64 delayspartitioned 5 ps by 5 ps in a range of 840 ps up to 1160 ps, in additionto the foregoing embodiment.

At first, the selector 15 selects the one-period mode 51, and the delaygenerator 10 outputs 64 delay signals of the clock signal 18 partitioned5 ps by 5 ps in a range of 340 ps up to 660 ps like the foregoingembodiment.

And, as shown in FIG. 21, the phase comparator 11 compares a secondleading edge 41 of the clock signal 18 that is an object of measurementwith each of 64 leading edges of the output of the delay generator 10partitioned 5 ps by 5 ps as to which edge rose ahead, with the firstleading edge 40 of the two-GHz clock signal 18 that is an object ofmeasurement of the periodic jitter assumed to be a starting point,thereby measuring the clock period of a one-period portion.

Continuously, the selector 15 selects the two-period mode 52, and thedelay generator 10 outputs 64 delay signals of the clock signal 18partitioned 5 ps by 5 ps in a range of 840 ps up to 1160 ps like theforegoing embodiment.

And, as shown in FIG. 21, the phase comparator 11 compares a thirdleading edge 53 of the clock signal 18 that is an object of measurementwith each of 64 leading edges of the output of the delay generator 10partitioned 5 ps by 5 ps as to which edge rose ahead, with the firstleading edge 40 of the two-GHz clock signal 18 that is an object ofmeasurement of the periodic jitter assumed to be a starting point,thereby measuring the clock period of a two-period portion.

The analysis section firstly finds the periodic jitter of a one-periodportion and the periodic jitter of a two-period portion of the clock,based upon the period of a one-period portion and the period of atwo-period portion of the clock that are a measurement resultrespectively. And, it analyzes Jmeas and Jmeas_n from these periodicjitter of a one-period portion and periodic jitter of a two-periodportion of the clock. The measurement result in the one-period modecorresponds to EQ. 1, and the measurement result in the two-period modecorresponds to EQ. 2 (n=2). The analysis section solves the simultaneousequations of EQ. 1 and EQ. 2, thereby finding only the periodic jitterof the clock signal 18 that is an object of measurement.

Embodiment 4

Next, a fourth embodiment in the present invention will be explained.

In the measurement circuit described in the above-mentioned embodiment,a signal that became a reference of measurement was generated from itsown clock signal to measure the periodic jitter of the clock signal bymeasuring timing discrepancy of the leading edge with this generatedsignal. However, in a case where the leading edge of the clock signal isswinging very slowly, such a swing is impossible to detect with a methodof measuring the periodic jitter, i.e. of measuring a time intervalbetween a certain leading edge and a leading edge next hereto asdescribed above. This is because the leading edge of the clock signalswings very slowly in a case where this periodic jitter is very small.So as to measure the swing of the leading edge that is very slow likethis, there is also case where timing jitter needs to be measured inaddition to the foregoing periodic jitter.

Thereupon, a case of measuring the timing jitter will be explained in afourth embodiment, by employing FIG. 22.

FIG. 22 is a block diagram of the fourth embodiment.

The measurement circuit in this embodiment is configured of a delaygenerator 10, a phase comparator 11, a priority encoder 12, a digitallow-pass filter 14, and a serialization circuit 16, and a calibrator 17.Additionally, identical codes are affixed to the components similar tothat of the first embodiment, and detailed explanation thereof isomitted.

A big difference with the foregoing embodiment lies in that not theclock signal 18 that is an object of measurement, but a reference clock54 is input into the delay generator 10.

The delay generator 10 outputs 64 delay signals of the clock signal 18partitioned 5 ps by 5 ps in a range of 340 ps up to 660 ps based uponthe reference clock 54 similarly to the foregoing measurement circuit.

The phase comparator 11 performs a process identical to that of theforegoing embodiment, and outputs the measurement result.

Embodiment 5

A method will be explained of measuring the timing jitter in aconfiguration different from that of the fourth embodiment as a fifthembodiment in the present invention, by employing FIG. 23.

As shown in FIG. 23, the measurement circuit in this embodiment isconfigured of a phase detector 60, a charge pump circuit 61, an A/Dconverter 62, a switch 63, and a capacity element 64.

The reference clock 54 and the clock signal 18 that is an object ofmeasurement are input into the phase detector 60. The phase detector 60outputs a phase difference (timing jitter) between the reference clock54 and the clock signal 18 that is an object of measurement, which wereinput, as a difference of the high-level interval by means of an upsignal 65 and a down signal 66.

Herein, an operation of the signal of the phase detector 60 will beexplained, by employing FIG. 24.

When the reference clock 54 rises, the down signal 66 also rises.

On the other hand, when the clock signal 18 that is an object ofmeasurement rises, the up signal 65 also rises.

And, when both of the up signal 65 and the down signal 66 rise, both ofthe up signal 65 and the down signal 66 trail after a constant time.

The charge pump circuit 61 is configured of two current sources 67, afirst switch 68, and a second switch 69 as shown in FIG. 23. The twocurrent sources 67 cause an identical current to flow respectively.

The up signal 65 from the phase detector 60 is input into a controlsignal of the first switch 68 of the charge pump circuit 61. On theother hand, the down signal 66 from the phase detector 60 is input intoa control signal of the second switch 69 of the charge pump circuit 61.The first switch 68 is switched on in a case where the up signal 65 isat a high level, and is switched off in a case where it is at a lowlevel, and the second switch 69 is switched on in a case where the downsignal 66 is at a high level, and is switched off in a case where it isat a low level.

As shown in FIG. 23, let a node between the first switch 68 and thesecond switch 69 be defined as a monitor node, and let an electricpotential of the monitor node as Vmoni. The input of an A/D converter62, the switch 63, and the capacity element 64 are connected to themonitor node. Another terminal of the switch 63 is connected to anelectric potential (Vdd/2) that is half the power source voltage. Thisswitch 63 is switched off in a case where the reference clock 54 is at ahigh level, and switched on in a case where it is at a low level.

Herein, an operation of Vmoni will be explained, by employing FIG. 24.

In a case where the clock signal 18 that was an object of measurementrose ahead of the reference clock 54 by ΔT, the up signal 65 rises aheadof the down signal 66 by ΔT, and both of the up signal 65 and the downsignal 66 trail after a constant time. For this, the interval in whichthe up signal 65 is at a high level becomes longer by ΔT than that ofthe down signal 66. As a result, the interval in which the first switch68 of the charge pump circuit 61 is switched on becomes longer by ΔTthan that of the second switch 69, which causes Vmoni to change fromVdd/2 to Vdd/2+IΔT/C. Where, I represents a current value that is causedto flow by the current source 67 of FIG. 23, and C represents a capacityvalue of the capacity element 64 of FIG. 23.

In a case where the reference clock 54 trailed, the switch 63 isswitched on, and Vmoni is initialized from Vdd/2+IΔT/C to Vdd/2.

Conversely, in a case where the clock signal 18 that was an object ofmeasurement rose behind the reference clock 54 by ΔT, the down signal 66rises ahead the up signal 65 by ΔT, and both of the up signal 65 and thedown signal 66 trail after a constant time. For this, the interval inwhich the down signal 66 is at high level becomes longer by ΔT than thatof the up signal 65. As a result, the interval in which the secondswitch 69 of the charge pump circuit 61 is switched on becomes longer byΔT than that of the first switch 68, which causes Vmoni to change fromVdd/2 to Vdd/2−IΔT/C. When the reference clock 54 trails, the switch 63is switched on, and Vmoni is initialized from Vdd/2−IΔT/C to Vdd/2.

Also, in a case where the clock signal 18 that was an object ofmeasurement and the reference clock 54 rose simultaneously, not only thedown signal 66 but also the up signal 65 rises simultaneously. For this,the interval in which the charge pump circuit 61 or the second switch 69is switched on runs short, and Vmoni remains Vdd/2.

As mentioned above, a phase difference ΔT of the leading edge betweenthe clock signal 18 that is an object of measurement and the referenceclock 54 can be converted into a voltage change amount proportional toΔT, which is IΔT/C, for measurement.

The foregoing measurement result of the measurement circuit is convertedinto six-bit digital data by the A/D converter 62.

Sampling of Vmoni to the A/D converter 62 is carried out ahead of thetrailing of the reference clock 54 by T1 with a sampling signal 70, asshown in FIG. 24. Also, upon letting a lower limit of an input range ofthe A/D converter 62 be defined as Vmin, an upper limit as Vmax, and amaximum value of the jitter that is required to measure as ΔTmax,designing I and C so that Vmin<Vdd/2−IΔTmax/C, and Vdd/2+IΔTmax/C<Vmaxmakes it possible to prevent the measurement result of the jitter fromexceeding the input range of the A/D converter 62.

The analysis section calculates a phase difference between the clocksignal and the reference signal based upon the output from the A/Dconverter 62, and analyzes the timing jitter.

The advantage of this embodiment lies in that an area is easy tominiaturize because the delay generator 10 and the phase comparator 11are unnecessary, and that a filter process is easy like that of thelow-pass filter because the measurement result is output as an analoguevoltage value as compared with the fourth embodiment.

Embodiment 6

The measurement circuit for measuring the jitter was explained in theforegoing embodiments.

The measurement circuit for measuring the noise will be explained inthis embodiment. Additionally, identical codes are affixed to aconfiguration similar to that of the foregoing embodiment, and detailedexplanation thereof is omitted. Also, the measurement circuit of thisembodiment is realized by a technology of a power source voltage of 1.0V, and a 90-nm CMOS process. Also, the power source line is employed asan object of measurement for explanation in this embodiment; however itis not limited hereto. That is, in order to check the noise thatpropagates through a board, a signal line such as the groundingconductor also may be employed.

FIG. 25 is a measurement circuit for measuring the noise in thisembodiment.

As shown in FIG. 25, the measurement circuit in this embodiment isconfigured of a high-pass filter 71, a voltage comparator 72, a D/Aconverter 73, and a ring oscillator 74.

The periodical power source noise is an object of measurement, and thenoise that occurs only once is impossible to measure because anm-out-of-n sampling measurement is employed in the power source noisemeasurement circuit. Also, information as to whether the power sourcenoise exceeded a certain voltage value can be output; however a powersource noise waveform is impossible to measure. A clock frequency of thecircuit that is an object of measurement of the power source noise is2.5 GHz, so the periodical power source noise of 2.5 GHz need to bemeasured.

The high-pass filter 71 is connected to a power source line 75 that isan object of measurement of the power source noise, a direct currentcomponent of the power source noise is deleted, and only the highfrequency component is input into the voltage comparator 72.

A sampling signal 70 for deciding a timing at which the voltagecomparator 72 makes a comparison is generated in the ring oscillator 74,and is input into the voltage comparator 72. A plurality of kinds ofreference voltages 76 to be employed at the moment that voltagecomparator 72 makes a comparison are generated in the D/A converter 73,and are input into the voltage comparator 72. The voltage comparator 72makes a voltage comparison between an input 77 having the low frequencycomponent cut away and the voltages of a reference voltage 76 at theinstant of the trailing of the sampling signal 70.

Accordingly, the maximum value and the minimum value of the power sourcenoise can be known from a comparison result between each of a pluralityof kinds of the reference voltages 76, and the voltage of a power sourceline 75 that is an object of measurement of the power source noise,which come from this measurement circuit, so amplitude of the powersource noise can be known; however the direct current component isimpossible to measure.

Herein, in this embodiment, the reason why the high-pass filter 71 isnecessary will be explained.

Assume that the voltage range of the power source noise of the powersource line 75 that is an object of measurement is 1.0 V±0.3 V.Inputting this power source noise directly into the voltage comparator72 without going through the high-pass filter 71 necessitatespreparation of the reference voltage 76 of 1.0 V±0.3 V. But, in the LSIof the power source voltage 1.0 V, the reference voltage 76 less than1.0 V is easy to generate; however the reference voltage 76 equal to ormore than 1.0 V is difficult to generate. Accordingly, so as to measurethe power source noise with the reference voltage 76 less than 1.0 V,the direct current component of the power source noise that is an objectof measurement has to be lowered. Accordingly, lowering the directcurrent component necessitates the high-pass filter 71.

A configuration of the high-pass filter 71 is shown in FIG. 26.

Three resistance elements 80 are connected in series between the powersource line and the grounding conductor. Assume that the values of thesethree resistance elements 80 are identical. Also, a capacity element 64is connected between an input 79 and the output 19. The direct currentcomponent of the power source noise that is an input is a power sourcevoltage 1 V. However, the direct current component of the output 19 ofthe high-pass filter 71 can be lowered to 0.66 V that is two-thirds thepower source voltage. The values of the resistance element 80 andcapacity element 64 that configure the high-pass filter 71 are set sothat the cut-off frequency of the high-pass filter 71 becomes lower thanthat of the measured frequency component of the power source noise.

73 is a D/A converter, and a six-bit reference voltage control signal 78is input into the D/A converter 73. The D/A converter 73 outputs thereference voltages 76 partitioned 10 mV by 10 mV in a range of 0.68V±0.32 V to the voltage comparator 72 as described above.

72 is a voltage comparator. A configuration of the voltage comparator 72is shown in FIG. 27.

The voltage comparator 72 is configured of an inverter 81, a switch 63,an n-type MOS transistor 82, and a synchronous set/reset flip-flop(hereinafter, referred to as an SR flip-flop 83).

The switch 63 is switched on in a case where the sampling signal 70 isat a high level, and is switched off in a case where it is at a lowlevel.

An inverted signal 70 b of the sampling signal is input into the SRflip-flop 83. Output data of the SR flip-flop 83 is not changed in acase where the sampling signal 70 is at a high level, but the outputdata of the SR flip-flop 83 is changed in a case where it is at a lowlevel.

An input 84 of the voltage comparator and the reference voltage 76 areconnected to gate electrodes of two n-type MOS transistors 82respectively.

An operation of the voltage comparator 72 will be explained, byemploying FIG. 28 and FIG. 29. FIG. 28 represents a case where thesampling signal 70 is at a high level, and FIG. 29 represents a casewhere the sampling signal 70 is at a low level.

In FIG. 28 that is a case where the sampling signal 70 is at a highlevel, the input and the output of the inverter 81 are in ashort-circuited status. Accordingly, an electric potential between afirst node 85 and a second node 86 is close to a threshold voltage ofthe inverter 81, and the inverter 81 is in an extremely sensitive stateto a change of the first node 85 and the second node 86.

Herein, a case where the input 84 of the voltage comparator 72 is higherthan the reference voltage 76 will be explained. In this case, theelectric potential of the first node 85 becomes lower slightly than thatof the second node 86 because the electric potentials of the first node85 and the second node 86 are not completely identical, and the input 84of the voltage comparator is higher than the reference voltage 76.

In FIG. 29 that is a case where the sampling signal 70 is at a lowlevel, the input and the output of each inverter 81 are separated, andtwo inverters 81 are latched. Specifically, the electric potential ofthe first node 85 connected to the reset input of the SR flip-flop 83 ischanged to a low-level one, and the electric potential of the secondnode 86 connected to the set input of the SR flip-flop 83 is changed toa high-level one. This causes the level of the output 19 of the SRflip-flop 83 to become high, which indicates that the input 84 of thevoltage comparator is higher than the reference voltage 76. Conversely,in a case where the input 84 of the voltage comparator is lower than thereference voltage 76, the situation becomes opposite to the foregoing,that is, the level of the output 19 of the SR flip-flop 83 becomes low.

The voltage comparator 72 outputs the voltage value of the referencevoltage having the high level that was output from the output 19.

The noise measurement circuit explained in this embodiment can be alsoprovided with a peak value holding circuit 13, a digital low-pass filter14, a selector 15, a serialization circuit 16, an analysis section, amemory circuit, a monitor section, or an adjustment circuit similarly tothe foregoing jitter measurement circuit. Additionally, detailedexplanation of configurations similar to the foregoing configuration isomitted, and a configuration that differs is explained.

At first, the analysis section will be explained.

In a case where the analysis section analyzes amplitude of the noise, itcompares the maximum value and the minimum value to be output from thepeak value holding circuit, thereby analyzing the amplitude of thenoise.

In a case where the analysis section measures the maximum value and theminimum value of the noise amount, at first, it samples the output datafrom the serialization circuit 16. And, it compares the maximum value ofthe sampled measurement result with a basic value 0.68 V of thereference voltage, thereby analyzing the maximum value of the noiseamount. Similarly, the analysis section compares the minimum value ofthe sampled measurement result with the basic value 0.68 V of thereference voltage, thereby analyzing the minimum value of the noiseamount.

In a case where the analysis section analyzes the frequency component ofthe noise, the real-time oscilloscope 44 of the analysis sectionmeasures its all measurement results as digital data, and outputs itsmeasurement data to the personal computer 45. Making a Fourier transformof the digital data on the personal computer 45 allows a frequencycomponent 46 of the noise to be obtained.

Next, a method will be explained of reducing the noise based upon theanalyzed noise.

As shown in FIG. 30, the semiconductor integrated circuit apparatus isconfigured of a power source line 121, a power source noise measurementcircuit 92, a power source noise reduction circuit 120, and a measureddata process circuit 112. Additionally, this noise measurement circuit120 includes the foregoing measurement circuit and analysis section.

The power source noise measurement circuit 92 and the power source noisereduction circuit 120 are connected to the power source line 121. Apower source noise measurement result 122 obtained in the power sourcenoise measurement circuit 92 is input into the power source noisereduction circuit 120. The foregoing noise measurement circuit isemployed as the power source noise measurement circuit 92 forexplanation; however the noise measurement circuit having anotherconfiguration may be employed. As the power source noise reductioncircuit 120 is used, for example, an NMOS transistor shown in FIG. 31.

The problem exists that when the power source noise reduction circuit120 is caused to operate, the power source noise decreases; however thepower consumption augments. Thereupon, the measured data process circuit112 outputs a control signal 123 for causing the power source noisereduction circuit 120 to operate if the measured power source noise islarger than a desired value, and outputs a control signal 123 forcausing the power source noise reduction circuit 120 to stop if themeasured power source noise is smaller than a desired value. Changingon/off of the power source noise reduction circuit 120 dynamically in aloop of the power source noise measurement circuit 92, the power sourcenoise reduction circuit 120, and the measured data process circuit 112makes it possible to take a feedback control so that the powerconsumption by the power source noise reduction circuit 120 is minimizedwhile the power source noise is suppressed to a desired value. As aresult, minimizing a penalty of the power consumption by the powersource noise reduction circuit 120 is made possible while the powersource noise is suppressed to a desired value.

The foregoing voltage comparator 72 is excellent in being able toperform a comparative operation even in a high-speed operationcondition, i.e., at 2.5 GHz. Thus, there are two reasons why the latchis fast. The first reason is that the latch is carried out at a highspeed because the input nodes of the two inverters 81, to which theinput 84 of the voltage comparator and the reference voltage 76 werealready interrupted, do not receive an influence by a change in theinput 84 of the voltage comparator and the reference voltage 76 duringthe interval from a comparison start up to the time that the twoinverters 81 are latched to settle the comparison result. The secondreason is that the latch is carried out at a high speed because a powersupply to the two inverters 81 is made at any time without interruption.

By the way, when the reference voltage 76 of the foregoing power sourcenoise measurement circuit fluctuates due to the power source noise thatis an object of measurement, validity of the measurement result of thepower source noise is lost. For this, the power source noise of themeasurement circuit itself has to be prevented. Thereupon, as shown inFIG. 32, a power source filter 91 is inserted between a power sourceline 90 of the measurement circuit and the power source line 75 that isan object of measurement of the power source noise. This makes itpossible to prevent the power source noise that is an object ofmeasurement from breaking into the power source line 90 of themeasurement circuit, and to stabilize the power sourceelectric-potential of the measurement circuit 92.

Specifically, the power source filter 91, which is configured of aresistance element 80 between the power source line 90 of the powersource noise measurement circuit and the power source line of thecircuit that is an object of measurement of the power source noise, anda capacity element 64 between the power source line 90 of the powersource noise measurement circuit and the grounding conductor, has afunction of the low-pass filter. The values of the resistance element 80and the capacity element 64 configuring the low-pass filter are set sothat the cut-off frequency of the low-pass filter becomes ten times lessthan the clock frequency or less of the circuit that is an object ofmeasurement of the power source noise.

Employing the foregoing power source filter 91 eliminates a necessityfor the dedicated power source supply to the measurement circuit 92,which enables the cost to become low.

Embodiment 7

Next, a seventh embodiment in the present invention will be explained,by employing FIG. 33. A noise measurement circuit having a differentconfiguration from that of the foregoing sixth embodiment will beexplained in the seventh embodiment. Additionally, identical codes areaffixed to components similar to that of the sixth embodiment, anddetailed explanation thereof is omitted.

As shown in FIG. 33, the power source noise measurement circuit in thisembodiment is configured of a voltage comparator 72, a D/A converter 73,a ring oscillator 74, and a booster 93. A difference with the foregoingsixth embodiment lies in that the high-pass filter 71 was deleted to addthe booster 93. The advantage of the seventh embodiment lies in thatthis allows not only the amplitude of the power source noise but alsothe direct current component to be measured.

The booster 93 generates a voltage of 1.32 V higher than the powersource voltage 1.0 V, and outputs it to the D/A converter 73. The D/Aconverter 73 outputs the reference voltages 76 partitioned 10 mV by 10mV in a range of 1.0 V±0.32 V. The voltage comparator 72 makes a sizecomparison between the voltage of the power source line 75 that is anobject of measurement of the power source noise and the referencevoltage 76, thereby allowing information as to whether the power sourcenoise exceeded the reference voltage 76 to be output. The voltagecomparator 72 outputs the comparison result.

Embodiment 8

An eighth embodiment of the present invention will be explained, byemploying FIG. 34.

A noise measurement circuit having a different configuration from thatof the foregoing sixth and seventh embodiments will be explained in theeighth embodiment. Additionally, identical codes are affixed tocomponents similar to that of the sixth and seventh embodiments, anddetailed explanation thereof is omitted.

As shown in FIG. 34, the noise measurement circuit is configured of ahigh-pass filter 71, a voltage comparator 72, and a D/A converter 73. Adifference with the foregoing sixth embodiment lies in that the ringoscillator 74 was deleted to employ the voltage comparator 72 requiringno sampling signal.

The advantage of this embodiment lies in that this allows not only theperiodical power source noise but also the noise that occurs only onceto be measured. But, in this embodiment, information as to whether thepower source noise exceeded the reference voltage 76 can be output;however the power source noise waveform is impossible to measure.

Embodiment 9

A ninth embodiment of the present invention will be explained, byemploying FIG. 35.

A noise measurement circuit having a different configuration from thatof the foregoing eighth embodiment will be explained in the ninthembodiment. Additionally, identical codes are affixed to componentssimilar to that of the eighth embodiment, and detailed explanationthereof is omitted.

As shown in FIG. 35, the power source noise measurement circuit in theninth embodiment is configured of a high-pass filter 71, 64 voltagecomparators 72, and an analogue voltage generator 94. A difference withthe foregoing eighth embodiment lies in making the number of the voltagecomparator 72 and the output plural, and in replacing the D/A converterwith the analogue voltage generator 94. The advantage of this embodimentlies in that the power source noise waveform can be measured in a realtime basis.

The analogue voltage generator 94 outputs 64 reference voltages 76 eachof which differs by 10 mV from the other in a range of 0.68 V±0.32 V.The reference voltages 76 each of which differs by 10 mV from the otherare input into 64 voltage comparators 72 respectively. A size comparisonresult between the voltage of the power source line 75 that is an objectof measurement of the power source noise and the reference voltage 76 inthe voltage comparator 72 is output as 64-bit digital data.

Herein, a method will be explained of measuring the power source noisewaveform in a real time basis, by employing FIG. 36.

A size comparison result 102 between a power source noise waveform 100that is an object of measurement and a first reference voltage 101 makesit possible to know the time when the power source noise becameidentical to the first reference voltage 101. Similarly, a sizecomparison result 104 between the power source noise waveform 100 thatis an object of measurement and a second reference voltage 103 makes itpossible to know the time when the power source noise became identicalto the second reference voltage 103. Also, a size comparison result 106between the power source noise waveform 100 that is an object ofmeasurement and a third reference voltage 105 makes it possible to knowthe time when the power source noise became identical to the thirdreference voltage 105.

In such a manner, in this embodiment, piling up all comparison resultsof 64 reference voltages 76, each of which differs by 10 mV from theother in a range of 0.68 V±0.32 V, makes it possible to measure thepower source noise waveform at a resolution of 10 mV in a real timebasis.

Additionally, a case of measuring the noise waveform in a real timebasis was described in this embodiment; however the priority encoder maybe provided to output only the position of the most significant bithaving the high-level noise waveform output like the foregoing firstembodiment.

Embodiment 10

A case will be explained of measuring stress of the chip in thisembodiment.

FIG. 37 is a block diagram of the measurement circuit in thisembodiment.

As shown in FIG. 37, the measurement circuit is a ring oscillatorcircuit that is comprised of the inverters of which the stage number isodd.

FIG. 38 is a block diagram of an inverter circuit.

As shown in FIG. 38, the inverter circuit is a CMOS inverter circuit.Examples of a layout pattern A and a layout pattern B of this CMOSinverter circuit are shown in FIG. 39 and FIG. 40 respectively. Thelayout pattern B is a layout pattern obtained by rotating the layoutpattern A by 90 clockwise.

The measurement circuit having the layout pattern of FIG. 39 and themeasurement circuit having the layout pattern of FIG. 40 are mounted inplural on an identical chip to that of the semiconductor integratedcircuit that is an object of measurement as shown in FIG. 41.Additionally, a configuration is more favorable in which a plurality ofsets, each of which has one measurement circuit having the layoutpattern of FIG. 39 and one measurement circuit having the layout patternof FIG. 40, are mounted on the chip.

A signal in which the high level and the low level are repeated as shownin FIG. 42 is output from the measurement circuit configured in such amanner. Normally, in a case where no stress exists on the chip, theoutput signal of each measurement circuit ought to coincide with that ofthe other. Accordingly, measuring the output signal of each measurementcircuit allows the stress to be measured.

The measurement circuit explained in this embodiment can be alsoprovided with an analysis section, a memory circuit, a monitor section,or an adjustment circuit similarly to the foregoing measurementscircuit. Additionally, detailed explanation of configurations similar tothe foregoing configuration is omitted, and a configuration that differsis explained.

At first, the analysis section will be explained.

The analysis section measures the number of times by which the highlevel and the low level of the output signal sent out from eachmeasurement circuit are repeated for a unit time, i.e. the frequency.And, it measures a frequency difference between the output signal fromeach measurement circuit and the output signal from the other, andanalyzes the stress of the chip.

Continuously, the monitor section will be explained.

The monitor section judges that the chip was stressed abnormally when afrequency difference between the output signal from each measurementcircuit analyzed in the analysis section and the output signal from theother exceeded a threshold, and sends a malfunctional signal out to theMPU on the identical chip.

Embodiment 11

A measurement circuit for measuring a temperature of the chip having thesemiconductor integrated circuit mounted will be explained in thisembodiment. Additionally, the measurement circuit of this embodimentemploys the foregoing ring oscillator, so identical codes are affixed tothe similar configuration, and detailed explanation thereof is omitted.Additionally, in a case of measuring the temperature of the chip, as tothe layout pattern of the inverter circuit, either pattern may beemployed.

The measurement circuit outputs a signal in which the high level and thelow level are repeated as shown in FIG. 42. Measuring the frequency ofthis output signal allows the temperature of a transistor (element) tobe known. This reason is that when the frequency falls below a certainthreshold, it can be recognized that a delay occurred in repetition ofthe high level and the low level of the output signal because thetemperature of the transistor (element) becomes high.

The measurement circuit explained in this embodiment can be alsoprovided with an analysis section, a memory circuit, a monitor section,or an adjustment circuit similarly to the foregoing measurementscircuit. Detailed explanation of configurations similar to the foregoingconfiguration is omitted, and a configuration that differs is explained.

The analysis section measures the frequency from the output signal sentout from the measurement circuit. When this frequency falls below acertain threshold, the monitor section recognizes that the delayoccurred in the repetition of the high level and the low level of theoutput signal, and sends the malfunctional signal out to the MPU on theidentical chip because the temperature of the transistor (element)becomes high. The MPU that received the malfunctional signal sendswarning information out.

Also, the analysis section compares the frequency of each measurementcircuit with that of the other respectively, and analyzes dispersion ofperformance of the transistor (element).

Embodiment 12

A configuration of measuring a leakage current of the semiconductorintegrated circuit will be explained in this embodiment.

Leakage current measurement circuits are mounted in plural on the chipas shown in FIG. 41.

FIG. 43 is a block diagram of the leakage current measurement circuit.

A transistor 421 is for monitoring the leakage current. When the leakagecurrent is caused to flow in this transistor 421, the current value ofits leakage current is reflected in Imoni. The A/D converter convertsthe current value of Imoni into a digital value, and outputs it as ameasured leakage current value.

The measurement circuit explained in this embodiment can be alsoprovided with an analysis section, a memory circuit, a monitor section,or an adjustment circuit similarly to the foregoing measurementscircuit. Detailed explanation of configurations similar to the foregoingconfiguration is omitted, and a configuration that differs is explained.

At first, the analysis section will be explained. The analysis sectionanalyzes the leakage current value that is a measurement result of aplurality of the measurement circuits, and makes an analysis as to whichelement of the semiconductor integrated circuit or thereabouts has theleakage current produced.

Continuously, the monitor section will be explained.

The monitor section judges that abnormality occurred in the chip whenthe leakage current value exceeded a threshold, and sends themalfunctional signal out to the MPU on the identical chip.

Embodiment 13

As a rule, current consumption of LSI changes at all times responding toan operational pattern of the LSI. Accordingly, the power source noiseand the jitter of the clock signal also change at all times respondingto the operational pattern of the LSI. For this, there is a case wherean LSI operational fault occurs only when the LSI executed a certainspecific operation. Thereupon, inevitability exists for clarifying acorrelation between the operational pattern of the LSI and the noise orthe jitter by making an actual measurement thereof. A thirteenthembodiment of the present invention enabling this will be explained, byemploying FIG. 44.

As shown in FIG. 44, a circuit 140 and a circuit 141 that are an objectof measurement are mounted on an identical chip of an identical LSI 142.Additionally, one of the foregoing measurement circuits is employed forthe measurement circuit 141.

An operational control signal 143 for indicating a start of theoperation of the circuit 140 that is an object of measurement is inputinto the measurement circuit 141 as well. This makes it possible tomeasure the physical amount that exerts an influence upon the circuit140 that is an object of measurement in a certain specific operationalinterval of the circuit 140 that is an object of measurement.

Additionally, a configuration may be made to input this operationalcontrol signal 143 into the memory circuit as well. In this case, aconfiguration is made to affix operation identification information foruniquely identifying the operation operational control signal byoperational control signal, and to store it correspondingly to themeasurement result.

Embodiment 14

A measurement result management system for managing the measurementresult measured by the foregoing measurement circuit will be explainedin this embodiment.

FIG. 45 is a conceptual view of the measurement result management systemof the present invention.

The measurement result management system is configured of asemiconductor integrated circuit apparatus 4501 and a management server4502.

The semiconductor integrated circuit apparatus 4501 is an apparatusmounted on an end-user such as a customer. Also, the semiconductorintegrated circuit apparatus 4501 has a semiconductor integrated circuit4503, a measurement circuit 4504, a memory circuit 4505, and atransmission section 4506.

The measurement circuit 4504 was configured on the identical chip tothat of the semiconductor integrated circuit 4503. Also, the measurementcircuit 4504 measures various physical amounts such as the jitter of thesignal in the semiconductor integrated circuit 4503 that is actuallyoperating, the swing of the power source (noise), the temperature, thepower (the leakage current, an ON-state current, etc.), the dispersionof the device performance, and the stress of the chip. Additionally, notonly the measurement operation of the measurement circuit 4504 may beperformed at any time while the power source is applied to the chip, butalso it may be performed intermittently, for example, once per oneminute, and it is not limited hereto.

The memory circuit 4505 accumulates the measurement result from themeasurement circuit 4504. Further, the memory circuit 4505 storesidentification information for uniquely identifying the semiconductorintegrated circuit 4503. Additionally, the memory circuit 4505 may beconfigured not only on the identical chip to that of the semiconductorintegrated circuit 4503, but also outside the chip.

The transmission section 4506 is for transmitting data accumulated inthe memory circuit 4505 and identification information for uniquelyidentifying the above semiconductor integrated circuit 4503 to themanagement server 4502. Additionally, not only the transmission section4506 may be configured so that it causes the memory circuit 4505 toaccumulate a predetermined amount thereof, and transmit it predeterminedamount by predetermined amount, but also it may be configured totransmit the data accumulated in the memory circuit 4505 at apredetermined time, and also it is acceptable that it is configured totransmit it at the moment that a measured data transmission request wasreceived from the management server 4502.

Further, the transmission section 4506 may be configured to have anencryption section 4507. In this case, after the transmission section4506 encrypted the data accumulated in the memory circuit 4505 and theidentification information for uniquely identifying the abovesemiconductor integrated circuit 4501 in the encryption section 4507, ittransmits them. There are many methods of encryption; however thedetails thereof are omitted because they are known. Anyone may beemployed in the present invention.

The management server 4502 is a server mounted on a management companyfor managing the semiconductor integrated circuit apparatus 4501. Also,the management server 4502 has a reception section 4508, a managementsection 4509, a fault warning section 4510, and a display section 4511.

The reception section 4508 receives the measurement result to betransmitted from the semiconductor integrated circuit apparatus 4501,and the identification information for uniquely identifying the abovesemiconductor integrated circuit 4503. Additionally, in a case where theencryption section 4507 is configured in the transmission section 4506of the semiconductor integrated circuit apparatus 4501, and themeasurement result and the identification information for uniquelyidentifying the above semiconductor integrated circuit 4503 areencrypted and transmitted, a decoding section 4512 is provided in thereception section 4508, and the encrypted and transmitted measuredresult and identification information are decoded.

The management section 4509 manages the measurement result, which thereception section 4508 received, identification information byidentification information.

The fault warning section 4510 is for making a fault prediction from aperformance fluctuation and a change with time of the semiconductorintegrated circuit 4503 based upon the measurement result, which themanagement section 4509 is managing, to send warning information out.

The display section 4511 is for displaying the warning information fromthe fault warning section 4510.

An operation in this embodiment will be explained. Additionally, as oneexample, the measurement circuit 4504 for measuring the jitter of thesemiconductor integrated circuit 4503 that is an object of measurementis employed for explanation. Also, a case will be explained where thememory circuit 4504 is caused to accumulate the measurement result by apredetermined amount, which is transmitted predetermined amount bypredetermined amount.

The measurement circuit 4504 measures each temperature of the chiphaving the semiconductor integrated circuit 4503 mounted, which isactually operating. This measurement result is accumulated in the memorycircuit 4505. When the measurement result is accumulated by apredetermined amount in the memory circuit 4505, the transmissionsection transmits the measurement result accumulated in the memorycircuit 4505 to the management server 4502 together with theidentification information.

The transmitted measurement result is received in the reception section4508 of the management server 4502. The management section 4509 managesthe measurement result identification information by identificationinformation, based upon the received identification information.

When the fault warning section 4510 detects the measurement resultexceeding a predetermined value from among the measurement results thatthe management section 4509 is managing, or detects that a differencebetween continuous two measured values exceeded a predetermined value,it judges that abnormality has occurred in the semiconductor integratedcircuit apparatus 4501, and sends the warning information out. Thedisplay section 4511 displays the warning information from the faultwarning section.

Additionally, the foregoing semiconductor integrated circuit apparatuswas explained by employing a configuration having the memory circuit;however a configuration having only the measurement circuit is alsoacceptable. In this case, the transmission section is configured totransmit the measurement result whenever the measurement circuit makes ameasurement.

Also, the foregoing semiconductor integrated circuit apparatus may beconfigured to have the analysis section. In this case, the transmissionsection is configured to transmit the analysis result that the analysissection analyzed.

Further, the case was explained where one measurement circuit wasmounted on the semiconductor integrated circuit apparatus in theforegoing embodiment; however a plurality thereof may be mounted. Inthis case, the memory circuit is configured to correspondingly store themeasurement circuit identification information for uniquely identifyingthe measurement circuit, and the measurement result of the abovemeasurement circuit.

Further, the case was explained where the memory circuit was mounted onthe identical chip to that of the semiconductor integrated circuit inthe foregoing embodiment; however it may be mounted outside the chip. Inthis case, the memory circuit is configured to correspondingly store theidentification information for uniquely identifying the abovesemiconductor integrated circuit, and each of the measurement resultsfrom a plurality of the chips.

Further, a configuration may be made so as to encrypt the measurementresult that the foregoing transmission section transmits. In this case,a configuration is made so that the encryption circuit is mounted priorto the transmission section, and the transmission section transmits themeasurement result that this encryption circuit encrypted.

Additionally, it is apparent that the invention is not intended to belimited to each of the above-mentioned embodiments, and variousmodifications may be made appropriately within the scope of thetechnical spirit of the present invention.

The foregoing present invention is applicable for the semiconductorintegrated circuit that requires that the physical amount, which exertsan influence upon the operation of the semiconductor integrated circuit,such as the noise or the jitter be measured.

Also, the foregoing present invention is applicable for thesemiconductor integrated circuit that requires that the physical amount,which exerts an influence upon the operation of the semiconductorintegrated circuit, such as the noise or the jitter be reduced aftermanufacturing the LSI.

Further, the foregoing present invention is applicable for theintegrated circuit that requires that the physical amount, which exertsan influence upon the operation of the semiconductor integrated circuit,such as the noise or the jitter be reduced by modifying anyone of theboard, the package, the power source system of the LSI.

In accordance with the present invention, mounting the variousmeasurement circuits for measuring the physical amount, which exerts aninfluence upon the actual operation of the semiconductor integratedcircuit, such as the noise or the jitter on the identical chip to thatof the semiconductor integrated circuit that is an object of measurementmakes it possible to measure the physical amount, which exerts aninfluence upon the actual operation of the semiconductor integratedcircuit, such as the noise or the jitter in the actual operation.

Also, feeding the obtained measurement result back to the circuit foradjusting the semiconductor integrated circuit that is an object ofmeasurement makes it possible to reduce the physical amount, whichexerts an influence upon the actual operation of the semiconductorintegrated circuit, such as the noise or the jitter even aftermanufacturing the semiconductor integrated circuit.

Further, converting the time-series measurement result into a frequencydomain to make an analysis with the frequency domain allows whichportion of the power source system of the board, the package, and theLSI should be modified to be known clearly, which makes it possible toefficiently find the countermeasure for reducing the noise or thejitter.

Further, the various factors that exert an influence upon the operationof the semiconductor integrated circuit that is really working (actualoperation) are analyzed and monitored, thereby making it possible toprevent the operational stop of the system beforehand.

Further, analyzing and managing the various factors that exert aninfluence upon the operation of the semiconductor integrated circuitthat is actually working makes it possible to reflect its analysis andmanagement in the next-generation semiconductor integrated circuit.

1. A management server arranged on an identical chip to that of a mainframe circuit that is an object of measurement, said management servermanaging a measurement result of said measurement circuit that istransmitted from a semiconductor integrated circuit apparatus having ameasurement circuit for measuring a physical amount of said main framecircuit at the time of an actual operation of said main frame circuit,having: reception means for receiving the transmitted measurementresult, and identification information for uniquely identifying saidmain frame circuit; and management means for managing said receivedmeasurement result identification information by identificationinformation.
 2. The management server according to claim 1, wherein in acase where the transmitted measurement result and identificationinformation were encrypted, said reception means have decoding means fordecoding the encrypted measurement result and identificationinformation.
 3. The management server according to claim 2, havingmonitor means for giving a fault warning of said main frame circuit,based upon the measurement result that said management means manage.